(1) Field of the Invention
The invention relates to cold cathode field emission devices and displays.
(2) Description of the Prior Art
Cold cathode electron emission devices are based on the phenomenon of high field emission wherein electrons can be emitted into a vacuum from a room temperature source if the local electric field at the surface in question is high enough. The creation of such high local electric fields does not necessarily require the application of very high voltage, provided the emitting surface has a sufficiently small radius of curvature.
The advent of semiconductor integrated circuit technology made possible the development and mass production of arrays of cold cathode emitters of this type. In most cases, cold cathode field emission displays comprise an array of very small conical emitters, each of which is connected to a source of negative voltage via a cathode conductor line or column. Another set of conductive lines (called gate lines) is located a short distance above the cathode lines at an angle (usually 90.degree.) to them, intersecting with them at the locations of the conical emitters or microtips, and connected to a source of relatively positive voltage.
The electrons that are emitted by the cold cathodes accelerate past openings in the gate lines and strike an electroluminescent panel that is located some distance above the gate lines. Thus, one or more microtips serves as a sub-pixel for the total display. The number of sub-pixels that will be combined to constitute a single pixel depends on the resolution of the display and on the operating current that is to be used. In general, even though the local electric field in the immediate vicinity of a microtip is in excess of 1 million volts/cm., the externally applied voltage is under a 100 volts. However, even a relatively low voltage of this order can obviously lead to catastrophic consequences, if short circuited.
The early prior art in this technology used external resistors, placed between the cathode or gate lines and the power supply, as ballast to limit the current in the event of a short circuit occurring somewhere within the display. While this approach protected the power supply, it could not discriminate between individual microtips or groups of microtips on a given cathode or gate line. Thus, in situations where one (or a small number) of the microtips is emitting more than its intended current, no limitation of its individual emission is possible. Such excessive emission can occur as a result of too small a radius of curvature for a particular microtip or the local presence of gas, particularly when a cold system is first turned on. Consequently the more recent art in this technology has taught ways of providing individual ballast resistors, either one per microtip or one per group of microtips.
A good example of the prior art is the approach taken by Meyer (U.S. Pat. No. 5,194,780 March 1993) as illustrated in FIG. 1. This shows, in plan view, a portion of a single cathode column which, instead of being a continuous sheet, has been formed into a mesh of lines 15 intersecting with lines 16. A resistive layer 17 has been interposed between the mesh and the substrate (not shown here). Microtips 12 have been formed on the resistive layer and located within the interstices of the mesh. A single gate line intersects the cathode line/mesh, and current from the mesh must first travel along resistive layer 17 before it reaches the microtips. A disadvantage of this approach is that the presence of the mesh limits the resolution of the display. Another disadvantage is that the ballast resistance value associated with any particular microtip can vary widely because of the geometry of this design.
A cross-sectional view of a somewhat larger portion of a Meyer style display is shown in FIG. 2. Buffer layer 21 sits atop substrate 22. Layer 27 is a resistive layer in which are embedded cathode columns 25. Gate lines 29 are separated from the cathode columns by dielectric layer 28 and are embedded in second resistive layer 23.
More recently, Kochanski (U.S. Pat. No. 5,283,500 Feb. 1, 1994) has described a variety of layout schemes which use a similar approach. Kochanski also teaches a method for ensuring that the ballast resistance associated with each of the various microtips is essentially the same. This is achieved by arranging the microtips in groups that are accessed by a symmetrical pattern of individual resistors, each of the same magnitude. Kochanski also uses a two impedance structure. The first impedance carries all the current associated with one or more intersecting regions. The second impedance is composed of a multiplicity of impedances each of which carries current from one or a few microtips at the given intersecting region(s). It is, however, not necessary to use this kind of two impedance structure.
From a cost standpoint the best design is that of Meyer. However, the problem remains that the value of the ballast resistance associated with any particular microtip can vary substantially from microtip to microtip. Recent studies have shown that the fraction of the microtips that are actually emitting in an arrangement similar to that described by Meyer is fewer than 9% and frequently is as low as 3%. This is believed to be due, at least in part, to this ballast non-uniformity problem. The present invention seeks to provide uniform ballast values while retaining the low cost features of the Meyer approach.
A pending application, ERSO-84-0029, unlike Kochanski's two impedance approach, has already addressed the problem by teaching that all the microtips in a given group are to be connected to an equipotential area which is, in turn, connected to a single ballast resistor. Two such devices are shown in schematic cross-section in FIG. 3. Microtips, such as 12, are in contact with equipotential area (conductive disk) 31 which lies on one end of resistor 32. Cathode columns 33 (running at right angles to the plane of the figure) lie on and connect to the other ends of resistors 32. Resistors, cathode columns, and equipotential areas are all covered by dielectric layer 34. Gate line 35 is deposited on top of layer 34 and openings, such as 36, are formed in it. Note that line 35 is conductive all the way from the openings 36 to the edge of the device. The openings extend through the dielectric layer down to the surface of equipotential area 31. A microtip 12 is centrally located inside each of the openings. A problem with this design is that although higher current densities are achieved because each microtip is associated with a ballast resistor of the same value, there is no resistor between the gate openings and the gate electrodes. Since, in FEDs, the gate current is much less than the cathode current, it is advantageous to have a resistor connected to the gate electrode. Moreover, in the same way that it is necessary that a uniform resistance value be associated with each microtip, it is also necessary that a uniform resistance value be associated with each gate. The present invention is directed towards including this feature in its design.